military and industrial temperature ranges idt54/74fct299t/at/ct fast cmos 8-input universal shift register 1 june 2002 military and industrial temperature ranges the idt logo is a registered trademark of integrated device technology, inc. ? 2002 integrated device technology, inc. dsc-2632/8 features: ? std., a, and c grades ? low input and output leakage 1a (max.) ? cmos power levels ? true ttl input and output compatibility: ?v oh = 3.3v (typ.) ?v ol = 0.3v (typ.) ? high drive outputs (-15ma i oh , 48ma i ol ) ? meets or exceeds jedec standard 18 specifications ? military product compliant to mil-std-883, class b and desc listed (dual marked) ? power off disable outputs permit "live insertion" ? available in the following packages: ? industrial: soic, qsop ? military: cerdip, lcc functional block diagram idt54/74fct299t/at/ct fast cmos 8-input universal shift register description: the fct299t is built using an advanced dual metal cmos technology. the fct299t is an 8-input universal shift/storage register with 3-state outputs. four modes of operation are possible: hold (store), shift left, shift right and load data. the parallel load inputs and flip-flop outputs are multiplexed to reduce the total number of package pins. additional outputs are provided for flip-flops q 0 and q 7 to allow easy serial cascading. a separate active low master reset is used to reset the register. c d d c p q c d d c p q c d d c p q c d d c p q c d d c p q c d d c p q c d d c p q c d d c p q i/o 6 i/o 5 i/o 4 i/o 3 i/o 2 i/o 1 i/o 0 i/o 7 q 7 ds 7 oe 2 oe 1 mr q 0 cp ds 0 s 1 s 0
military and industrial temperature ranges 2 idt54/74fct299t/at/ct fast cmos 8-input universal shift register pin configuration symbol description max unit v term (2) terminal voltage with respect to gnd ?0.5 to +7 v v term (3) terminal voltage with respect to gnd ?0.5 to v cc +0.5 v t stg storage temperature ?65 to +150 c i out dc output current ?60 to +120 ma absolute maximum ratings (1) notes: 1. stresses greater than those listed under absolute maximum ratings may cause permanent damage to the device. this is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. exposure to absolute maximum rating conditions for extended periods may affect reliability. no terminal voltage may exceed vcc by +0.5v unless otherwise noted. 2. inputs and vcc terminals only. 3. output and i/o terminals only. symbol parameter (1) conditions typ. max. unit c in input capacitance v in = 0v 6 10 pf c out output capacitance v out = 0v 8 12 pf capacitance (t a = +25c, f = 1.0mhz) note: 1. this parameter is measured at characterization but not tested. cerdip/ soic/ qsop top view 2 3 1 16 15 14 11 19 18 20 17 13 12 5 6 7 4 8 9 10 i/o 6 oe 1 oe 2 v cc i/o 4 q 0 i/o 2 i/o 0 mr gnd s 1 i/o 7 ds 7 q 7 i/o 5 cp i/o 3 i/o 1 ds 0 s 0 1 2 3 4 5 7 9 6 8 10 11 12 13 14 15 16 17 18 19 20 i/o 7 ds 7 q 7 i/o 5 i/o 3 o e 2 o e 1 m r g n d d s 0 c p i / o 1 s 0 v c c s 1 index i/o 6 i/o 4 q 0 i/o 2 i/o 0 lcc top view function table (1) inputs mr s 1 s 0 cp response l x x x asynchronous reset q 0 ?q 7 = low hh h parallel load; i/o x q x hlh shift right; ds 0 q 0 , q 0 q 1 , etc. hh l shift left; ds 7 q 7 , q 7 q 6 , etc. h l l x hold note: 1. h = high voltage level l = low voltage level x = don?t care = low-to-high clock transition pin description p in names description c p clock pulse input (active edge rising) ds 0 serial data input for right shift ds 7 serial data input for left shift s 0 , s 1 mode select inputs mr asynchronous master reset input (active low) oe 1 , oe 2 3-state output enable inputs (active low) i/o 0 ?i/o 7 parallel data inputs or 3-state parallel outputs o 0 , o 7 serial outputs
military and industrial temperature ranges idt54/74fct299t/at/ct fast cmos 8-input universal shift register 3 symbol parameter test conditions (1) min. typ. (2) max. unit v ih input high level guaranteed logic high level 2 ? ? v v il input low level guaranteed logic low level ? ? 0.8 v i ih input high current (4) v cc = max. v i = 2.7v ? ? 1a i il input low current (4) v cc = max. v i = 0.5v ? ? 1 i i input high current (4) v cc = max., v i = v cc (max.) ? ? 1a v ik clamp diode voltage v cc = min., i in = ?18ma ? ?0.7 ?1.2 v i os short circuit current v cc = max., v o = gnd (3) ?60 ?120 ?225 ma v oh output high voltage v cc = min i oh = ?6ma mil 2.4 3.3 ? v in = v ih or v il i oh = ?8ma ind v i oh = ?12ma mil 2 3 ? i oh = ?15ma ind v ol output low voltage v cc = min i ol = 32ma mil ? 0.3 0.5 v v in = v ih or v il i ol = 48ma ind i off input/output power off leakage (5) v cc = 0v, v in or v o 4.5v ? ? 1a v h input hysteresis ? ? 200 ? mv i cc quiescent power supply current v cc = max. ? 0.01 1 ma v in = gnd or v cc dc electrical characteristics over operating range following conditions apply unless otherwise specified: industrial: t a = ?40c to +85c, v cc = 5.0v 5%; military: t a = ?55c to +125c, v cc = 5.0v 10% notes: 1. for conditions shown as min. or max., use appropriate value specified under electrical characteristics for the applicable dev ice type. 2. typical values are at v cc = 5.0v, +25c ambient. 3. not more than one output should be tested at one time. duration of the test should not exceed one second. 4. the test limit for this parameter is 5a at t a = ?55c. 5. this parameter is guaranteed but not tested.
military and industrial temperature ranges 4 idt54/74fct299t/at/ct fast cmos 8-input universal shift register notes: 1. for conditions shown as min. or max., use appropriate value specified under electrical characteristics for the applicable dev ice type. 2. typical values are at v cc = 5.0v, +25c ambient. 3. per ttl driven input; (v in = 3.4v). all other inputs at v cc or gnd. 4. this parameter is not directly testable, but is derived for use in total power supply calculations. 5. values for these conditions are examples of ? i cc formula. these limits are guaranteed but not tested. 6. i c = i quiescent + i inputs + i dynamic i c = i cc + ? i cc d h n t + i ccd (f cp /2+ f i n i ) i cc = quiescent current ? i cc = power supply current for a ttl high input (v in = 3.4v) d h = duty cycle for ttl inputs high n t = number of ttl inputs at d h i ccd = dynamic current caused by an input transition pair (hlh or lhl) f cp = clock frequency for register devices (zero for non-register devices) f i = output frequency n i = number of outputs at f i all currents are in milliamps and all frequencies are in megahertz. power supply characteristics symbol parameter test conditions (1) min. typ. (2) max. unit ? i cc quiescent power supply vcc = max. ? 0.5 2 ma current ttl inputs high v in = 3.4v (3) i ccd dynamic power supply current (4) vcc = max. v in = v cc ? 0.15 0.25 ma/mhz outputs open v in = gnd oe 1 = oe 2 = gnd mr = v cc s 0 = s 1 = v cc ds 0 = ds 1 = gnd one input toggling 50% duty cycle i c total power supply current (6) vcc = max. v in = v cc ? 1.5 3.5 ma outputs open v in = gnd f cp = 10mhz 50% duty cycle oe 1 = oe 2 = gnd mr = v cc s 0 = s 1 = v cc ds 0 = ds 7 = gnd v in = 3.4v ? 2 5.5 one bit toggling v in = gnd at f i = 5mhz 50% duty cycle vcc = max. v in = v cc ? 3.8 7.3 (5) outputs open v in = gnd f cp = 10mhz 50% duty cycle oe 1 = oe 2 = gnd mr = v cc s 0 = s 1 = v cc ds 0 = ds 7 = gnd v in = 3.4v ? 6 16.3 (5) eight bits toggling v in = gnd at f i = 2.5mhz 50% duty cycle
military and industrial temperature ranges idt54/74fct299t/at/ct fast cmos 8-input universal shift register 5 switching characteristics over operating range idt54fct299t idt54/74fct299at idt54/74fct299ct mil. ind. mil. ind. mil. symbol parameter condition (1) min . (2) max . min . (2) max . min . (2) max . min . (2) max . min . (2) max . unit t plh propagation delay c l = 50pf 2 14 2 7.2 2 9.5 2 6.5 2 7.5 ns t phl cp to q 0 or q 7 r l = 500 ? t plh propagation delay 2 12 2 7.2 2 9.5 2 6.5 2 7.5 ns t phl cp to i/ox t phl propagation delay 2 10.5 2 7.2 2 9.5 2 6.5 2 7.5 ns mr to q 0 or q 7 t phl propagation delay 2 15 2 8.7 2 11.5 2 6.5 2 7.5 ns mr to i/ox t pzh output enable time 1.5 15 1.5 6.5 1.5 7.5 1.5 6.5 1.5 7.5 ns t pzl oe x to i/ox t phz output disable time 1.5 9 1.5 6 1.5 6.5 1.5 6 1.5 6.5 ns t plz oe x to i/ox t su set-up time high or low 7.5 ? 3.5 ? 4 ? 3.5 ? 4 ? ns s 0 or s 1 to cp t su set-up time high or low 5.5 ? 4 ? 4.5 ? 4 ? 4.5 ? ns i/on, ds 0 or ds 7 to cp t h hold time high or low 1 ? 1 ? 1 ? 1 ? 1 ? ns s 0 or s 1 to cp t h hold time high or low 1.5 ? 1.5 ? 1.5 ? 1.5 ? 1.5 ? ns i/ox, ds 0 or ds 7 to cp t w cp pulse width, high or low 7 ? 5 ? 6 ? 5 ? 6 ? ns t w mr pulse width low 7 ? 5 ? 6 ? 5 ? 6 ? ns t rem recovery time 7 ? 5 ? 6 ? 5 ? 6 ? ns notes: 1. see test circuit and waveforms. 2. minimum limits are guaranteed but not tested on propagation delays.
military and industrial temperature ranges 6 idt54/74fct299t/at/ct fast cmos 8-input universal shift register pulse generator r t d.u.t . v cc v in c l v out 50pf 500 ? 500 ? 7.0v 3v 1.5v 0v 3v 1.5v 0v 3v 1.5v 0v 3v 1.5v 0v data input timing input asynchronous control preset clear etc. synchronous control t su t h t rem t su t h high-low-high pulse low-high-low pulse t w 1.5v 1.5v same phase input transition 3v 1.5v 0v 1.5v v oh t plh output opposite phase input transition 3v 1.5v 0v t plh t phl t phl v ol control input 3v 1.5v 0v 3.5v 0v output normally low output normally high switch closed switch open v ol 0.3v 0.3v t plz t pzl t pzh t phz 3.5v 0v 1.5v 1.5v enable disable v oh preset clear clock enable etc. octal link octal link octal link octal link octal link test circuits and waveforms propagation delay test circuits for all outputs enable and disable times set-up, hold, and release times pulse width notes: 1. diagram shown for input control enable-low and input control disable-high. 2. pulse generator for all pulses: rate 1.0mhz; t f 2.5ns; t r 2.5ns. test switch open drain disable low closed enable low all other tests open switch position definitions: c l = load capacitance: includes jig and probe capacitance. r t = termination resistance: should be equal to z out of the pulse generator.
military and industrial temperature ranges idt54/74fct299t/at/ct fast cmos 8-input universal shift register 7 ordering information idt xx temp. range xxxx device type xx package x process so q industrial options small outline ic quarter-size small outline package 8-input universal shift register 54 74 ? 55 c to +125 c ? 40 c to +85 c d l military options cerdip leadless chip carrier blank b industrial mil-std-883, class b fct 299t 299at 299ct corporate headquarters for sales: for tech support: 2975 stender way 800-345-7015 or 408-727-6116 logichelp@idt.com santa clara, ca 95054 fax: 408-492-8674 (408) 654-6459 www.idt.com 6/24/2002 updated as per pdns logic-00-07 and logic-01-04 data sheet document history
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